A non-volatile memory cell or an array of such cells is well known in the art. Typically, non-volatile memory cells are grouped in a sector and/or a block and all the cells within a sector or a block are erased simultaneously.
One particular type of non-volatile memory is a NAND cell array, wherein each sector or block in the array comprises many strings of stacked pairs of floating gates and control gates on top thereof. Between each pair of stacked pairs is an erase gate. See U.S. Pat. Nos. 6,885,586 and 6,992,929, whose disclosures are incorporated herein by reference in their entirety. See also “Split-Gate NAND Flash memory At 120 nm Technology Node Featuring Fast programming and Erase” by C. Y. Shu et al, 2004 symposium on VLSI Technology Digest of Technical papers, p. 78-79, which is also referenced in FIGS. 1(a) and 1(b) of U.S. Pat. No. 7,247,907; both of there references are also incorporated herein by reference in their entirety.
Another type of non-volatile memory is a NOR cell array, wherein each sector or block in the array comprises many strings of memory cell pairs. Referring to FIG. 3a there is shown a cross-sectional view of a unit of NOR cells of the prior art. FIG. 3b is a schematic representation of the cell shown in FIG. 3a. Each pair of memory cells comprises of two stacks of floating gates (see FG0 and FG1 in FIG. 3a) and control gates on top (see CG0 and CG1) an erase gate in between (see EG1), and two other erase gate, which also serve as select gates, or word lines during read operation (see WL0 (aka EG0) and WL1 (EG2)), on two other sides of the two stacks of floating gates and control gates on top. There is also a bit line contact between each two pairs of the 2-cell pairs.
In this type of memory cell, however, during erase operation, all of the erase gates in a cell or in an erase block are electrically connected together and the same erase voltage is applied to all of the erase gates in the erase block.
It is also well known in the prior that erase efficiency is proportional to the erase coupling ratio. As the erase coupling ratio is reduced, erase efficiency is increased.
Thus, it is one of object of the present invention to increase the erase efficiency by decreasing the erase coupling ratio.
Another object of the present invention is to improve the write-erase endurance performance. This type of memory cell is usually erased by tunneling electrons through a layer of inter-poly dielectric from a floating gate to an erase gate. During tunneling, a small portion of electrons are usually trapped in the inter-poly dielectric layer and, thus, increases the potential barrier to retard electron tunneling. When the trapped electrons accumulate to build up a high enough potential barrier after a certain write-erase cycles, erase can not be performed with the same applied erase voltage, which causes the memory cell to fail operation. The present invention allows the memory cell to switch to the other group of erased gate and/or increase the erase voltage for erase operation when the erase operation by the first group of erase gates fails, and the memory cell can continue functioning until more trapped electrons are built up.